| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 88 === Abstract
In this study, an analytical model of the positive Human Body Model Electro-Static Discharge (ESD) current distribution along the channel width is developed. The current distribution depends on the channel and well doping profiles, and the position relative to the well pick-up. In addition, a modified protection structure by the P+ stripes inserted into the N+ source regions was proposed to improve the ESD current uniformity.
In this study, a new method by the real-time I-V characteristics was used for the study of ESD transient phenomenon. We find that lower snapback voltage does not necessarily lead to higher ESD failure threshold. Instead of, the failure threshold depends on the average energy dissipation (Eave= VSP × IESD × Tduration / Aeff). Most important, energy consumption is dominated by the duration of snapback voltage but not by the duration of ESD current. It is also found that the floating gate transistors have the shorter duration of snapback voltage and larger snapback voltage.
Based on the analytical model, it is found that the channel profile with super steep retrograde well (SSRW) will lead to the worse ESD current uniformity. Moreover, it is also found that the SSRW profile also degrades the gate oxide integrity (GOI) and hot carrier effect (HCE). Therefore, a modified integrated process flow was proposed in a sub-quarter micron technology with dual gate oxide processes. It can be achieved by the method of blanking PW implant to de-couple the core and I/O transistors. Combining the use of modified LDD scheme with he modified ESD protection structure, we can compromise the ESD performance, GOI and HCE.
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