| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 88 === The demand of wireless communication grows rapidly in recent years. However the price of equipments for wireless transmission must be cheap enough so that customers can afford it. The goal of this work is to design and implement a low-cost FSK baseband receiver for indoor wireless communication systems.
A RF front-end down-converts the RF signal to IF stage. The IF is located at 750kHz. IF of 10.7MHz is evaluated incorporated with subsampling and single sideband image rejection. IF signal is sampled at a rate of 8MHz by a slicer. Down conversion circuit translates signal from 750kHz to baseband. Balanced quadri-correlator changes the deviation of frequency to the magnitude of amplitude. Decision circuit finally decides the signal whether is logic-1 or logic-0. In order to combat carrier frequency drift through wireless transmission, an automatic frequency control (AFC) loop is adopted to compensate carrier frequency drifts between the transmitter and receiver. The AFC loop is a frequency-locked loop (FLL), which consists of frequency discriminator, loop filter and numerical-controlled oscillator (NCO). Early-late timing recovery is used to get the optimum sampling phase and recover data rate.
Chip implementation obeys the design flow suitable to system designer and time of system implementation can be reduced. System simulation is complete by Matlab and SPW is used to fixed-pointed system simulation. VHDL code is derived from SPW and logic synthesis is achieved by Synopsys. The floorplan, placement and routing of the chip is complete by Candence. The chip uses Avant! standard-cell library and is fabricated with TSMC 0.35 1P4M CMOS technology. The data rate is targeted at 200kbps and the chip operates at 8MHz and 3.3V power supply. The designed low-IF baseband architecture is suitable for integration with RF front-end and A/D converter in a single chip in the future.
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