| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 88 === In this thesis, we present a bit-serial array for modular multiplication which is based on a modified Montgomery algorithm to fulfill the most famous RSA public-key crytosystem. Each basic unit is with 128bits, but we can combine those units to build a large-bit RSA cryptosystem. Because the signal-broadcasting problem is avoided, the proposed array can operate at high clock rate. RSA can be used in variety of Electronic Funds Transfer applications as well as other electronic banking and data handling applications where data must be encrypted
To realize the prototype chip of this design, we used Verilog-XL, Xillinx tools and Synopsys library to implement and simulate. We use FPGA (XILINX 4044XLA-09-HQ160, 0.35µm CMOS process, 3.3v power supply) to carry out it. The gate count is 27934. The operating clock rate is 100MHz. Data throughput is about 372k bits/sec.
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