The Study and Implementation of Digital Phase-Locked Loop Oscillator

• Main Authors: Mao-Sheng Yeh, 葉茂盛
• Other Authors: Jeng-Rern Yang
• Format: Others
• Language: zh-TW
• Published: 2000
• Online Access: http://ndltd.ncl.edu.tw/handle/76744205981541233077

碩士 === 元智大學 === 電機工程研究所 === 88 === In this thesis, we develop a digital phase-locked loop oscillator based on the theory of all-digital phase-locked loop (ADPLL). We propose a “modified phase detector” to replace a tradition phase detector. The design of the negative feedback system is theoretically simulated. We evaluate the system response with difference system parameter. Especially we use the theory to analyze the performance of digital loop filter with P controller or PD controller, and we practically implement the digital phase-locked loop oscillator with P controller. The digital phase-locked loop oscillator perform high spurious and high phase noise, so It is not suitable for local oscillator in communication application, but with the advantage of programmable loop filter, it can be applied to voltage-controlled oscillator (VCO) testing system or motor speed controlling system. The new idea for VCO testing is based on ADPLL technique. In order to test all kinds of VCOs, we need a programmable PLL to maintain the feedback system stably and properly. Therefore, we apply the ADPLL technique to VCO testing system. In this paper, we also practically implement the VCO testing system. The microprocessor controls the ADPLL system to force the DUT (VCO) to be locked in a designated frequency. If the tested VCO is locked at this frequency correctly, then the lock indicator will send the locking signal back to the microprocessor. The microprocessor will then receive the output voltage data of the loop filter. The microprocessor repeats the same procedures at the next testing frequency. The microprocessor will then record the oscillating frequency with different tuning voltage.