The Study and Implementation of Digital Phase-Locked Loop Oscillator
碩士 === 元智大學 === 電機工程研究所 === 88 === In this thesis, we develop a digital phase-locked loop oscillator based on the theory of all-digital phase-locked loop (ADPLL). We propose a “modified phase detector” to replace a tradition phase detector. The design of the negative feedback system is th...
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ndltd-TW-088YZU004420262016-01-29T04:19:40Z http://ndltd.ncl.edu.tw/handle/76744205981541233077 The Study and Implementation of Digital Phase-Locked Loop Oscillator 數位式鎖相迴路振盪器之研製 Mao-Sheng Yeh 葉茂盛 碩士 元智大學 電機工程研究所 88 In this thesis, we develop a digital phase-locked loop oscillator based on the theory of all-digital phase-locked loop (ADPLL). We propose a “modified phase detector” to replace a tradition phase detector. The design of the negative feedback system is theoretically simulated. We evaluate the system response with difference system parameter. Especially we use the theory to analyze the performance of digital loop filter with P controller or PD controller, and we practically implement the digital phase-locked loop oscillator with P controller. The digital phase-locked loop oscillator perform high spurious and high phase noise, so It is not suitable for local oscillator in communication application, but with the advantage of programmable loop filter, it can be applied to voltage-controlled oscillator (VCO) testing system or motor speed controlling system. The new idea for VCO testing is based on ADPLL technique. In order to test all kinds of VCOs, we need a programmable PLL to maintain the feedback system stably and properly. Therefore, we apply the ADPLL technique to VCO testing system. In this paper, we also practically implement the VCO testing system. The microprocessor controls the ADPLL system to force the DUT (VCO) to be locked in a designated frequency. If the tested VCO is locked at this frequency correctly, then the lock indicator will send the locking signal back to the microprocessor. The microprocessor will then receive the output voltage data of the loop filter. The microprocessor repeats the same procedures at the next testing frequency. The microprocessor will then record the oscillating frequency with different tuning voltage. Jeng-Rern Yang 楊正任 2000 學位論文 ; thesis 0 zh-TW |
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碩士 === 元智大學 === 電機工程研究所 === 88 === In this thesis, we develop a digital phase-locked loop oscillator based on the theory of all-digital phase-locked loop (ADPLL). We propose a “modified phase detector” to replace a tradition phase detector. The design of the negative feedback system is theoretically simulated. We evaluate the system response with difference system parameter. Especially we use the theory to analyze the performance of digital loop filter with P controller or PD controller, and we practically implement the digital phase-locked loop oscillator with P controller.
The digital phase-locked loop oscillator perform high spurious and high phase noise, so It is not suitable for local oscillator in communication application, but with the advantage of programmable loop filter, it can be applied to voltage-controlled oscillator (VCO) testing system or motor speed controlling system. The new idea for VCO testing is based on ADPLL technique. In order to test all kinds of VCOs, we need a programmable PLL to maintain the feedback system stably and properly. Therefore, we apply the ADPLL technique to VCO testing system.
In this paper, we also practically implement the VCO testing system. The microprocessor controls the ADPLL system to force the DUT (VCO) to be locked in a designated frequency. If the tested VCO is locked at this frequency correctly, then the lock indicator will send the locking signal back to the microprocessor. The microprocessor will then receive the output voltage data of the loop filter. The microprocessor repeats the same procedures at the next testing frequency. The microprocessor will then record the oscillating frequency with different tuning voltage.
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author2 |
Jeng-Rern Yang |
author_facet |
Jeng-Rern Yang Mao-Sheng Yeh 葉茂盛 |
author |
Mao-Sheng Yeh 葉茂盛 |
spellingShingle |
Mao-Sheng Yeh 葉茂盛 The Study and Implementation of Digital Phase-Locked Loop Oscillator |
author_sort |
Mao-Sheng Yeh |
title |
The Study and Implementation of Digital Phase-Locked Loop Oscillator |
title_short |
The Study and Implementation of Digital Phase-Locked Loop Oscillator |
title_full |
The Study and Implementation of Digital Phase-Locked Loop Oscillator |
title_fullStr |
The Study and Implementation of Digital Phase-Locked Loop Oscillator |
title_full_unstemmed |
The Study and Implementation of Digital Phase-Locked Loop Oscillator |
title_sort |
study and implementation of digital phase-locked loop oscillator |
publishDate |
2000 |
url |
http://ndltd.ncl.edu.tw/handle/76744205981541233077 |
work_keys_str_mv |
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