Slicing Floorplan Design with Boundary-Constrained Modules

• Main Authors: En-Cheng Liu, 劉恩誠
• Other Authors: Ting-Chi Wang
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/40573009668675267759

碩士 === 中原大學 === 資訊工程研究所 === 89 === We consider in this thesis the problem of slicing floorplan design with boundary-constrained modules. We develop a quadratic-time method that correctly transform a slicing floorplan into one that satisfies all given boundary constraints. This transformation method is then incorporated into a simulated annealing process to seek for a best possible solution. Unlike any other existing algorithm such as the one in [10], our floorplanning algorithm is always able to generate solutions satisfying all given boundary constraints, which is the major advantage of our algorithm over the algorithm in [10]. Our algorithm has been implemented in C language, and tested on two MCNC examples: ami33, ami49. When optimizing the area alone, our algorithm improved the average area up to 9.38% and 2.97% for ami33 and ami49, respectively, over the algorithm in [10]. Meanwhile the average interconnect wirelength was also improved by our algorithm up to 6.9% and 15.64% for ami33 and for ami49, respectively. When optimizing both area and interconnect wirelength, our algorithm was able to improve the average area up to 4.88% for ami33, 4.48% for ami49, and to improve the average wirelength up to 8.53% for ami33, 10.87% for ami49. As for the run time, our algorithm took less than one minute for almost all test cases.