VLSI Circuit Partitioning and Placement for Low Power Design

• Main Authors: Hsien-Wen Chang, 張獻文
• Other Authors: Mely Chen-Chi
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/54530305117538899733

碩士 === 中原大學 === 資訊工程研究所 === 89 === Power consumption is an important issue in VLSI circuit design. In this paper, we use quadrisection algorithm based on F-M partitioning, and the gain update scheme proposed in [1] to perform our partitioning process. Then, we use iterative partitioning to complete placement. In the partitioning and placement process, wire load power consumption is concerned to reduce total power, and gate load power consumption is added in the constraint to obtain uniform power distribution. The experimental result shows that, concerning switching rate in the cost function computing can reduce total wire load power consumption. Except area constraint, if gate load power constraint is added, we can distribute gate load power consumption uniformly and reduce the conjunction of high switching rate nets. Further more, we also think of high switching and high fanout nets especially clock net. After the cost of clock is multiplied by a weight(>1), we can not only reduce the power of the clock net but also reduce the total power. Experimental results are shown.