VLSI Implementation of An Area Efficient 2-D DCT/IDCT Architecture
碩士 === 逢甲大學 === 自動控制工程學系 === 89 === There are many efficient VLSI architectures of 2-D DCT and 2-D IDCT for area and processing speed points of view. However, most of them spend much cost for using in a real-time digital video codec system. The aim of our research work was to develop an area efficie...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/36736917762404073846 |