Design and Implementation of High-Performance Embedded Multimedia Microprocessor

• Main Authors: Yung-Chun Tseng, 曾詠淳
• Other Authors: Yau-Hwang Kuo
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/32429524247707377051

碩士 === 國立成功大學 === 資訊工程研究所 === 89 === In this thesis, the computation requirements of multimedia applications are analyzed first. According to the analysis result, we evaluate the performance of ARM. Obviously, the capability of ARM can not sufficiently support multimedia computations. To satisfy the computation requirements of multimedia applications, we propose an architecture of a highly integrated multimedia microprocessor. The proposed multimedia microprocessor integrates ARM-based architecture with multimedia functional unit (MFU) which is modified from the MFU of the micro-architecture of NSC98. The MFU not only supports the multimedia applications, but also features higher performance than the Intel MMX. Moreover, Z-buffer and alpha blending are two algorithms used in computer graphics frequently. To enhance the processing capability of the proposed multimedia microprocessor in computer graphics, two additional graphics instructions of MFU are designed to support the two algorithms. With these enhancements, we expect that the proposed multimedia microprocessor will meet the performance requirements in many kinds of multimedia applications. The total microarchitecture of the proposed multimedia microprocessor is modeled by Verilog hardware description language (HDL), and the COMPASS 0.35μm cell library and Synopsys EDA tool are adopted to synthesize it. Finally, by using MPEG video decompression, MPEG audio decompression and alpha blending algorithm as benchmarks, the performance analysis exhibits that the proposed multimedia microprocessor features higher performance than ARM by more than two times. 1.1 Background and Motivation 1.2 Organization of Thesis Chapter 2. Architecture of Embedded Multimedia Microprocessor (EMM) 2.1 The Overall Architecture 2.2 MFU 2.2.1 Original MFU 2.2.2 Enhanced MFU 2.3 Instruction Set 2.3.1 ARM Instruction Set 2.3.1.1 Data Processing 2.3.1.2 Multiply and Multiply-Accumulate 2.3.1.3 Single Data Transfer 2.3.1.4 Branch 2.3.2 MFU Instruction Set 2.3.2.1 Arithmetic Instructions 2.3.2.2 Comparison Instructions 2.3.2.3 Conversion Instructions 2.3.2.4 Logical Instructions 2.3.2.5 Shift Instructions 2.3.2.6 Graphics Instructions 2.4 Design Skills Chapter 3. RTL Realization of EMM 3.1 Pipeline 3.2 RTL Fetch Unit 3.3 RTL Instruction Decoder 3.4 RTL Register File 3.5 RTL Shifter 3.6 RTL MFU 3.6.1 ALU 3.6.2 Multiplier 3.6.3 Shifter 3.6.4 Converter 3.6.5 Sort Unit 3.6.6 Linear Interpolation Unit 3.7 Synthesis Results 3.8 Simulation Results Chapter 4. Performance Evaluation 4.1 Inverse Discrete Cosine Transform (IDCT) 4.1.1 IDCT Evaluation in ARM Instruction Set 4.1.2 IDCT Evaluation in EMM Instruction Set 4.2 Reconstruction 4.2.1 Reconstruction Evaluation in ARM Instruction Set 4.2.2 Reconstruction Evaluation in EMM Instruction Set 4.3 Inverse Modified Discrete Cosine Transform (IMDCT) 4.3.1 IMDCT Evaluation in ARM Instruction Set 4.3.2 IMDCT Evaluation in EMM Instruction Set 4.4 Alpha Blending 4.4.1 Alpha Blending Evaluation in ARM Instruction Set 4.4.2 Alpha Blending Evaluation in EMM Instruction Set 4.5 Evaluation Results Chapter 5. Conclusion and Future Work 5.1 Conclusion 5.2 Future Work Reference Appendix