| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 89 === This thesis presents the design and implementation of L-band DAB downconverter RFICs, including LNA/mixer/AGC and phase-locked oscillator (PLO), in a standard 0.35m CMOS technology. The RF is from 1.452 to 1.492 GHz, the LO is at 1.28 GHz and the IF is from 172 MHz to 212 MHz. The single-stage LNA has 3.2 dB noise figure and only 3dB gain. The single-balanced mixer has 20dB noise figure , 16dB conversion loss. Simulation results of the 1.28 GHz PLO show that the output power is —2 dBm and the locking time is 15s. An external hybrid-circuit LNA with 26 dB gain and 2.2 dB noise figure is added, due to the low gain result of the implemented LNA RFIC. The LNA and a 250 MHz IF lowpass filter with the LNA/mixer/AGC RFIC construct a hybrid/RFIC downconverter (not including the PLO RFIC) for receiving measurement. The hybrid/RFIC downconverter has 13dB gain, 3.5 dB noise figure, -17 dBm P1dB and —7.5 dBm OIP3. For 1.2Msps 32-QAM digital modulation, the measured error vector magnitude (EVM) is 1.2%. With a DAB test encorder and a DAB test receiver for OFDM signal receiving test, the adjacent channel power ratio (ACPR) is —30.61 dBc and the sensitivity is -90dBm (BER=10-4 ) or -97dBm (BER=10-2 ). Further effort will be devoted to design and implement a complete CMOS L-band DAB downconverter RFIC.
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