Implemenation and Formal Verification of 64-bit Pipelined Floating Point Unit
碩士 === 國立交通大學 === 資訊科學系 === 89 === In this thesis, we present an implemented design "Floating Point Unit", and extend Chen and Bryant's method to verify a pipelined arithmetic circuit. First, implement a 64-bit pipelined Floating Point Unit that suppor...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72816588406463752429 |