Implementation Of A Zero Skew Clock Tree Routing System

• Main Authors: Tai-Ling Chen, 陳泰霖
• Other Authors: Yirng-An Chen
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/71955871414480008029

碩士 === 國立交通大學 === 資訊科學系 === 89 === This thesis presents a set of techniques for developing a zero skew clock routing system with a BB partitioning method and a DME heuristic method proposed by Dr. K. D. Boese, Dr. A. B. Kahng, Dr. T.-H. Chao, Dr. Y.-C. Hsu, and Dr. J.-M. Ho in high-speed VLSI designs. The clock routing framework has three key components. The first component employs a DME (Deferred-Merge Embedding) algorithm to construct a clock tree topology and to determine best internal node locations. The routing construction is based on a balanced partitioning method. Thus the second component is a partitioning method called BB to separate a group into two subgroups which have almost the same loads. The third component will process the part of detailed routing. These schemes together give a good enhancement in convenient usage and performance to build a zero clock routing result.