| Summary: | 碩士 === 國立交通大學 === 電子工程系 === 89 === In this thesis, a CMOS two-step A/D converter with digital error correction circuit is described. The main components, coarse comparators and fine comparators, are designed and analyzed in detail. The reference voltage generator is a resistor ladder that divides the top and the bottom reference voltages. The D/A converter utilizes a switch box merged with the voltage generator, instead of using an operation amplifier. The top and the bottom reference voltages are 1V and 0V, respectively. So, the input voltage range of the A/D converter is from 0V to 1V. The simulation results performed by HSPICE show that the A/D converter achieves 8-bit resolution at 50M sampling rate when the supply voltage is 3.3V.The A/D converter is implemented by a 1P4M 0.35um CMOS process. The chip area of the A/D converter with pad is only 1.4mm x 1.3 mm because the capacitors in the A/D converter are formed by PMOS. The chip has been tested and the power consumption without output buffers at 3.3V, 50MSample/s is less than 40mW.
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