A Technology Mapping Algorithm for CPLD Architectures

• Main Authors: Shin-Liang Chen, 陳世梁
• Other Authors: TingTing Hwang
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/38725139604636936234

碩士 === 國立清華大學 === 資訊工程學系 === 89 === In this thesis, we propose a technology mapping algorithm for CPLD architectures. Our algorithm proceeds in two phases: mapping for single-output PLAs and packing for multiple-output PLAs. In the mapping phase, based on the results in [4], we propose a Look-Up-Table (LUT) based mapping algorithm. We will take advantage of existing LUT mapping algorithms for area and depth minimization. We also study, for a given (i, p, o)-PLA block structure, the problem of selecting the values of input and product term constraints for mapping for single-output PLA. Benchmark results show that our algorithm produce better results in terms of area and depth as compared to those by TEMPLA.