A Gbps AES Cipher
碩士 === 國立清華大學 === 資訊工程學系 === 89 === We propose an efficient hardware architecture of the AES encryption/decryption algorithm. The architecture can achieve high-speed data transfer up to 8 bits/cycles, which is 15 times faster than a Pentium III 600. In our design, the I/O of the proposed architectur...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54560364848496704120 |
| Summary: | 碩士 === 國立清華大學 === 資訊工程學系 === 89 === We propose an efficient hardware architecture of the AES encryption/decryption algorithm. The architecture can achieve high-speed data transfer up to 8 bits/cycles, which is 15 times faster than a Pentium III 600. In our design, the I/O of the proposed architecture is reduced to 8 bits and the I/O port is serialized. It provides a simple and useful I/O interface for host. A better methodology of key schedule is involved. A pipeline stage doubles the performance. Besides, DFT is also considered. We have successfully implemented it using Compass cell library targeted at 0.35μm TSMC SPTM CMOS process. The die size of the chip is 4.5x4.5 mm2, and the maximum frequency is up to 125MHz. This AES cipher can be applied to such areas as a security for gigabit speed networks.
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