| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 89 === In this thesis, we take the picoJava-II processor as an example to explore the implementation issues of an IC design in a deep sub-micron design environment. During the implementation process, we acquire experience so that similar problems can be avoided in the future. By taking the RTL code of the design as the input, we went through the typical cell-based design flow to realize its layout using 0.35 um technology. The functionality, timing, and power dissipation are also verified to ensure the quality of the implementation.
For CMOS technology, the size of transistor has been relentlessly scaling down following the Moore's Law. During this trend, the interconnection delay has been identified as one of the most critical factor in high-performace designs. To reduce the interconnecton delay, it is known that physical design process including the floorplanning, placement, and routing plays an important role. To explore the capability of commercial Automatic Placement and Routing (APR) tool, we build a method to finish the implementation of PicoJava-II. Our experimental results show that the result of PicoJava-II processorr.
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