The Implement of a 1536 bits RSA Encryption/Decryption Chip
碩士 === 國立海洋大學 === 電機工程學系 === 89 === It is obviously that security issues will play an important role in the majority of future computer and communication systems. Cryptographic algorithms and their software/hardware implementations are the major tools to achieve the system security. In th...
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| Format: | Others |
| Language: | zh-TW |
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2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/51664063897658558255 |
| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 89 === It is obviously that security issues will play an important role in the majority of future computer and communication systems. Cryptographic algorithms and their software/hardware implementations are the major tools to achieve the system security.
In this thesis, a 1536 bits RSA encryption/decryption chip based on the Montgomery algorithm is presented. The main structure of this chip includes an encryption/decryption module and a 64K*32 SRAM. The 32 bits encryption/ decryption module is implemented using Altera EFP10K200SRC240-1. Based on the same structure, a 1536 bits encryption/decryption module can be constructed easily using Altera EP20k400EBC 652-1 and has the expected 8.86 Kbps baud rate at the 40.83 clock rate.
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