| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 89 === Power dissipation and chip area are becoming an increasingly important issue in the design of analog-to-digital converter (ADC) as signal processing systems move into applications requiring portability, such as video applications. This research focuses on minimizing power dissipation and chip area in high resolution and high speed pipelined ADC.
In this thesis, we design a 10-bit, and 40MSamples/s three stages pipelined CMOS ADC. The ADC is implemented by a 3-stage pipelined architecture with a resolution of 4-b/stage for digital error correction to obtain a 10-bit resolution at a sampling rate of 40MHz. The main sub-circuits of the ADC are sample-and-hold circuit, 4-bit flash A/D converter, 4-bit D/A converter, subtractor, gain circuit, clock generator, encoder, register, and digital error correction. The sample-and-hold circuit is implemented with switched-capacitor techniques. Switched-capacitor requires only relative accurate capacitance. It is therefore much easier to be fabricated for processing technology. The post-simulation results show that the overall circuit of ADC has 40MHz sampling rate, ±0.5LSB differential non-linearity, and ±1LSB integral non-linearity.
The three-stage pipelined ADC is fabricated with UMC 0.5μm 2P2M n-well CMOS technology. The input range of the ADC is ±1.25V. The chip dissipates 180mW from a ±2.5V supply. Total layout area is 1800 × 1800μm2. The ADC can be applied to charge-coupled device (CCD) applications. Therefore, an idea of system on chip (SOC) for CCD applications was brought up at last.
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