Design of Efficient VLSI Architectures:Multiplier, 2-D Digital Filter, and Adaptive Digital Filter

• Main Authors: Lan-Da Van, 范倫達
• Other Authors: Wu-Shiung Feng
• Format: Others
• Language: en_US
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/21849845445622361753

博士 === 國立臺灣大學 === 電機工程學研究所 === 89 === In this dissertation, we propose several efficient very-large-scale-integration (VLSI) architectures and algorithms including fixed-width multipliers, two-dimensional (2-D) digital filter, and delay least-mean-square (DLMS)-based as well as recursive-least-squares (RLS)-based adaptive digital filters. First, a general methodology for designing lower-error area-efficient fixed-width two’s-complement multipliers that receive two -bit numbers and produce an -bit product is proposed. While keeping different columns in the subproduct array, we propose several better and realizable error-compensation biases to reduce truncation error by properly choosing the proposed binary thresholding and generalized indices. Therefore, several lower-error area-efficient fixed-width multipliers suitable for VLSI implementation can be obtained. Furthermore, these new multipliers with better error-compensation circuits are suited to the fractional multiplication through a scaling box. Second, 2-D systolic-array infinite-impulse-response (IIR) and finite-impulse-response (FIR) digital filter architectures without global broadcast by the hybrid of a modified reordering scheme and a new systolic transformation are presented. This architecture possesses local broadcast, lower quantization error and zero latency without sacrificing the number of multipliers as well as delay elements under the satisfactory critical period. In addition, we extend this new architecture to a useful 2-D systolic cascade-form architecture and provide the comprehensive error analysis for the proposed architectures. Third, we propose an efficient systolic architecture for the DLMS adaptive FIR digital filter based on a new tree-systolic processing element ( ) and an optimized tree-level rule. Applying our tree-systolic , a higher convergence rate than that of the conventional DLMS structures can be obtained without sacrificing the properties of the systolic-array architecture. The efficient systolic adaptive FIR digital filter not only operates at the highest throughput in the word-level but also considers finite driving/update of the feedback error signal. Furthermore, based on our proposed optimized tree-level rule that takes account of minimum delay and high regularity, an efficient N-tap systolic adaptive FIR digital filter can be easily determined under the constraint of maximum driving of the feedback error signal. Finally, we focus on developing a new relaxed Givens rotation (RGR)-RLS algorithm to pipeline the RGR-RLS systolic array. The novel systolic adaptive architecture has faster convergence rate than that of the least-mean-square (LMS) and the DLMS-based adaptive filters. On the other hand, an arbitrarily high throughput due to the fine-grain pipelining and square-root free computation can be achieved.