| Summary: | 碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === Abstract
The thesis proposes a chip design of burst-error-correcting Viterbi decoder. The decoder can be applied to both random and burst error channels. Firstly, We propose two new algorithms. One is a burst-error-alarm algorithm that is employed to detect the burst errors and another is burst-error-recovery algorithm that uses the recovery circuit to replace the data mixed with burst error. And then send the recovery information to the Viterbi decoder again to correct the random error in the recovery information.
To implement above algorithms, we use 0.35μm 1P4M Silicide to design a (2,1,7)(Q=8) burst-error-correcting Viterbi decoder chip. This decoder are composed of three circuits blocks. One is a (2,1,7) Viterbi decoder, one is burst-error-alarm/ burst-error-recovery circuit and the other is control circuit. The chip contains 630K transistors and occupies the area of 3.0 mm by 3.1 mm. Experimental results show that the decoder can achieve the decode rates of 106Mb/s on random error and 69.8Mb/s on burst error under 3.3 V. And the decoder has a net coding gain of 3.6 db at 10-4 bit error rate. Moreover, since we use modular and hierarchy design methodology, we can easily extend our architecture to higher bits VA decoder that will fit the requirement of modern communication system.
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