Chip Design of a Burst-Error-Correcting Viterbi Decoder
碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === Abstract The thesis proposes a chip design of burst-error-correcting Viterbi decoder. The decoder can be applied to both random and burst error channels. Firstly, We propose two new algorithms. One is a burst-error-alarm algorithm that...
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ndltd-TW-089TIT006520042015-10-13T12:10:00Z http://ndltd.ncl.edu.tw/handle/94074650062852055656 Chip Design of a Burst-Error-Correcting Viterbi Decoder 具突發錯誤更正之腓特比解碼器晶片設計 Wen-Hua Luo 駱文華 碩士 國立臺北科技大學 電腦通訊與控制研究所 89 Abstract The thesis proposes a chip design of burst-error-correcting Viterbi decoder. The decoder can be applied to both random and burst error channels. Firstly, We propose two new algorithms. One is a burst-error-alarm algorithm that is employed to detect the burst errors and another is burst-error-recovery algorithm that uses the recovery circuit to replace the data mixed with burst error. And then send the recovery information to the Viterbi decoder again to correct the random error in the recovery information. To implement above algorithms, we use 0.35μm 1P4M Silicide to design a (2,1,7)(Q=8) burst-error-correcting Viterbi decoder chip. This decoder are composed of three circuits blocks. One is a (2,1,7) Viterbi decoder, one is burst-error-alarm/ burst-error-recovery circuit and the other is control circuit. The chip contains 630K transistors and occupies the area of 3.0 mm by 3.1 mm. Experimental results show that the decoder can achieve the decode rates of 106Mb/s on random error and 69.8Mb/s on burst error under 3.3 V. And the decoder has a net coding gain of 3.6 db at 10-4 bit error rate. Moreover, since we use modular and hierarchy design methodology, we can easily extend our architecture to higher bits VA decoder that will fit the requirement of modern communication system. Wen-Ta Lee Chia-Chun Tsai 李文達 蔡加春 2001 學位論文 ; thesis 60 zh-TW |
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碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === Abstract
The thesis proposes a chip design of burst-error-correcting Viterbi decoder. The decoder can be applied to both random and burst error channels. Firstly, We propose two new algorithms. One is a burst-error-alarm algorithm that is employed to detect the burst errors and another is burst-error-recovery algorithm that uses the recovery circuit to replace the data mixed with burst error. And then send the recovery information to the Viterbi decoder again to correct the random error in the recovery information.
To implement above algorithms, we use 0.35μm 1P4M Silicide to design a (2,1,7)(Q=8) burst-error-correcting Viterbi decoder chip. This decoder are composed of three circuits blocks. One is a (2,1,7) Viterbi decoder, one is burst-error-alarm/ burst-error-recovery circuit and the other is control circuit. The chip contains 630K transistors and occupies the area of 3.0 mm by 3.1 mm. Experimental results show that the decoder can achieve the decode rates of 106Mb/s on random error and 69.8Mb/s on burst error under 3.3 V. And the decoder has a net coding gain of 3.6 db at 10-4 bit error rate. Moreover, since we use modular and hierarchy design methodology, we can easily extend our architecture to higher bits VA decoder that will fit the requirement of modern communication system.
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Wen-Ta Lee |
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Wen-Ta Lee Wen-Hua Luo 駱文華 |
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Wen-Hua Luo 駱文華 |
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Wen-Hua Luo 駱文華 Chip Design of a Burst-Error-Correcting Viterbi Decoder |
author_sort |
Wen-Hua Luo |
title |
Chip Design of a Burst-Error-Correcting Viterbi Decoder |
title_short |
Chip Design of a Burst-Error-Correcting Viterbi Decoder |
title_full |
Chip Design of a Burst-Error-Correcting Viterbi Decoder |
title_fullStr |
Chip Design of a Burst-Error-Correcting Viterbi Decoder |
title_full_unstemmed |
Chip Design of a Burst-Error-Correcting Viterbi Decoder |
title_sort |
chip design of a burst-error-correcting viterbi decoder |
publishDate |
2001 |
url |
http://ndltd.ncl.edu.tw/handle/94074650062852055656 |
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