Chip Design of a Burst-Error-Correcting Viterbi Decoder
碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 89 === Abstract The thesis proposes a chip design of burst-error-correcting Viterbi decoder. The decoder can be applied to both random and burst error channels. Firstly, We propose two new algorithms. One is a burst-error-alarm algorithm that...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2001
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| Online Access: | http://ndltd.ncl.edu.tw/handle/94074650062852055656 |