A High-Throughput Two-Dimension DCT/IDCT Architecturefor Real-Time Image and Video System and the VLSI Design

• Main Authors: Yi-Fang Chiu, 邱怡芳
• Other Authors: Jen-Shiun Chiang
• Format: Others
• Language: zh-TW
• Published: 2001
• Online Access: http://ndltd.ncl.edu.tw/handle/02188337381162056105

碩士 === 淡江大學 === 電機工程學系 === 89 === Discrete cosine transform (DCT) has been widely used in the implementation of low bit rate codecs for video compression and becomes an integral part of several international standards (such as JPEG, MPEG-X, H.26X, …). Since DCT takes lots of intensive computations, therefore, it is necessary to realize a cost-effective high speed DCT for video coding in VLSI chip. In this thesis, we propose a high throughput 2-D DCT/IDCT VLSI architecture for a real-time digital video codec system. Further,we propose to design and implement this DCT/IDCT to an intellectual property (IP) for the digital image data compressing. Besides, a new DCT/IDCT algorithm is developed by using row-column decomposition. We adapt (1) a table look-up method for multiplication can reduce hardware and increase the speed. (2) With a high throughput rate pipelined architecture and (3) row-column overlapped technique is used for this DCT/IDCT. Moreover, IP characteristic is considered in the arithmetic operation of this DCT/IDCT. Based on TSMC 0.35um 1P4M process parameters, COMPASS, a high performance cell library is for implementation of the proposed architecture. It integrates 119,181 transistors in a 4378.4um ´ 4378.4um chip area. Simulation results show the proposed architecture can work well with 100MHz which meets the requirement of many real-time digital video codec systems.