| Summary: | 碩士 === 大同大學 === 電機工程研究所 === 89 === This thesis presents a 3.3V, 1-GHz CMOS frequency synthesizer for mobile communications. This frequency synthesizer consists of a four-stage differential voltage-controlled oscillator with dual-delay scheme, a phase-frequency detector, a charge pump, a loop filter, a dual-modulus prescaler, and a divider.
The proposed voltage-controlled oscillator consists of four-stage fully differential delay cells performing full switching. With the negative skewed delay path, the oscillator can obtain higher frequency, and since normal delay path also exists, wider tuning range can be obtained. Since its differential structure, the VCO has better supply voltage phase noise. The VCO output range is 675MHz~1.1GHz and its gain is 223 MHz/V.
The frequency synthesizer is simulated by TSMC 0.35um CMOS technology. The HSPICE simulation results justify the feasibility of our proposed frequency synthesizer.
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