Architecture design, computer simulation and FPGA realization of^^blind carrier phase recovery for a 64-QAM demodulator

• Main Authors: CHUN-CHU CHEN, 陳春竹
• Other Authors: Thomas T. Fang
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/41846009459351488099

碩士 === 國立中正大學 === 電機工程研究所 === 90 === In this thesis, we discuss the very important subject of carrier phase synchronization as applied to communication systems using 64-QAM modulation. Under nonideal channel conditions including AWGN(Additive White Gaussian Noise) , the blind carrier phase recovery scheme we developed estimates the initial phase and track the phase difference between transmitter and receiver continuously . If the channel undergoes a sudden change causing the receiver to go out of lock , a lock indicator is designed in such a way as to be able to detect this situation and cause phase lock loop to relock automatically . Then we transform the algorithm into the hardware architecture using the optimal word length verified through computer simulation . After the hardware architecture is tansformed into VHDL , we use software tools including ModelSim , Simplify Pro and Xilinx for verification of the VHDL codes . At the end , we configure the FPGA chip and verify the emulation of FPGA chip by the use of appropriate instruments to complete the realization of the blind carrier phase recovery .