Design of a Decision Feedback Equalizer for IEEE 802.11b WLAN System
碩士 === 國立中興大學 === 電機工程學系 === 90 === In this thesis, design of a decision feedback equalizer (DFE) based on IEEE 802.11b protocol is presented. It has dual 6-tap feed-forward filters with 6-bit input and an 8-tap feedback filter with 2-bit input, that all the filters are implemented using...
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| Format: | Others |
| Language: | en_US |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82725817885192451197 |
| Summary: | 碩士 === 國立中興大學 === 電機工程學系 === 90 === In this thesis, design of a decision feedback equalizer (DFE) based on IEEE 802.11b protocol is presented. It has dual 6-tap feed-forward filters with 6-bit input and an 8-tap feedback filter with 2-bit input, that all the filters are implemented using the finite impulse response (FIR) filter. The output of the DFE is sliced into two levels by detector for CCK (8-chip complementary code keying) modulation. The least mean square (LMS) algorithm is used for updating the coefficients in the parallel DFE architecture. The data elapse time in the critical path is 19.46 nsec. The DFE is implemented using the TSMC 0.35 m CMOS 1p4m technology. The total gate count is 58624. The power consumption is 25.087 mW operating under a 3.3 V supply voltage.
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