Design of High-Speed CMOS Flash Analog-to-Digital Converter

• Main Author: 邱韋達
• Other Authors: 張振豪
• Format: Others
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/03881033608939533166

碩士 === 國立中興大學 === 電機工程學系 === 90 === The analog-to-digital conversion technique plays an important role in recent develop of integrated circuits, especially in data transmission circuits. A high-speed and precise A/D converter in systems can decrease the required specifications of the front-end and digital portion. This thesis describes the design of a 6-bit, differential and over 500MHz sampling rate A/D converter, which can sense 20mV voltage difference. In order to achieve high-speed and precise objective, we used the distributed S/H, preamplfier and the average technique to improve the relative non-linearity. In addition, the digital encoder is used to suppress the error rate. The flash A/D converter is designed using the in TSMC 0.35μm, 1P4M CMOS technology. HSPICE simulation results show that the A/D converter dissipates 700mW at 833MHz of sampling rate with 3.3V power supply.