A Low-Power SDRAM Controller on an8-bit RISC CPU
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === The fast growth of mobile computing and pocket computer has increased the effect of energy management in hardware design greatly. Memory chips occupies a great part of power consumption in an embedded system. There are several architectural approaches to impro...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2002
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| Online Access: | http://ndltd.ncl.edu.tw/handle/66874709772035348792 |
| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 90 === The fast growth of mobile computing and pocket computer has increased the effect of energy management in hardware design greatly. Memory chips occupies a great part of power consumption in an embedded system. There are several architectural approaches to improve SDRAM access latency and to reduce power consumption. In this thesis we present an effective power mode management scheme used in SDRAM memory controllers. The scheme employs a bus utilization monitoring mechanism to initiate proper operations of SDRAM chips. Our approach reduces energy consumption by actively
switching memories to low-power mode at low bus utilization. At higher bus utilization, the scheme switches memories to open page mode to reduce precharge energy as well as program execution time. This bus utilization monitor predictor reduces memory energy consumption by 26% without the expense of increasing program execution time.
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