Invoking two methods simultaneously for instruction level parallelism in Java

• Main Authors: Ming-Chun Chou, 周明俊
• Other Authors: Chung-Ping Chung
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/35304358048503061152

碩士 === 國立交通大學 === 資訊工程系 === 90 === Execution model of Java Virtual Machine architecture is a stack-based architecture. Because execution of Java method is restricted to the top of method stack, different method blocks cannot be executed in parallel even in traditional superscalar Java processor. Exploitation of instruction-level parallelism is restricted in the range of a single method block. We will break this restriction to execute two method blocks in parallel. In this thesis, we execute two method blocks in parallel by allowing to access method frames simultaneously. Before achieving this goal, we use method target predictor to get the start address of next method block and fetch the subsequent instructions without executing invoke instruction. In addition, method registers of next method block must be calculated early to access corresponding method frame simultaneously and we provide an argument passing mechanism for methods in order to achieve parallel execution of two methods correctly without using local variable. We also add additional design for reorder buffer to store two method blocks. The reorder buffer can be used to help to check the dependences of Java bytecode sequence due to argument passing relationship. Then, the modified superscalar Java processor can execute more instructions in parallel in a clock cycle than original superscalar Java processor. After analyzing our architecture, we evaluate the performance maximum speedup 2.8 of our proposed architecture versus traditional superscalar Java processor. Actual simulation result shows that our proposed superscalar Java processor could achieve the performance speedup of average 1.44. The performance variation of above speedup is due to timing of argument passing and the timing influences the opportunity of execution in parallel for method blocks. In hardware cost, we add a mechanism of method target prediction, additional fields of reorder buffer, two method registers and we add additional design for dependency checking in checking dependency between methods due to argument passing. Besides, we need not add extra hardware cost.