Logic Extraction from Transistor Level Circuit Netlists

• Main Authors: Lily Huang, 黃自立
• Other Authors: Jing-Yang Jou
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/07886149177730535745

碩士 === 國立交通大學 === 電子工程系 === 90 === The problem of finding subcircuits in a larger circuit arises in many contexts in computer-aided design. This is a problem currently solved by using various heuristics purely based on graph isomorphism. Such techniques, however, cannot utilize any circuit properties and usually lost the topological circuit structure, which led to failure in some cases such as shorting-input circuits. If the whole circuit needs to be represented in higher level models, it even takes numerous runs to extract every kind of subcircuits by these techniques. We present a logic extraction approach based on channel graph partition and modified circuit encoding algorithm. Without any pre-processing, it needs to traverse the input circuit only once, and converts the entire circuit netlist from transistor level to gate level. The reusability and efficiency are further achieved by using the elemental logic gates in standard cell library as the source of pattern circuits, and preparing the priori known pattern circuit information for identification off-line. The experiments on several real circuits containing sequential and combination logics show the near-linear performance in run time and memory usage.