The Design of Low Voltage Cascode LNAs for 2.4GHz Application

• Main Authors: Chih-Lung Hsiao, 蕭志龍
• Other Authors: Ro-Min Weng
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/39854248150107638132

碩士 === 國立東華大學 === 電機工程學系 === 90 === In the thesis, we present two ways to improve the cascode low noise amplifier (LNA) and to achieve better performance. The first way uses a fully differential LNA with Qenhancement circuit. We use an active cross-coupled pair as a Q-compensation circuit to generate negative conductance. The Q-compensation circuit can compensate the quality factor(Q) of the loading inductor. It makes the LNA achieve higher power gain. Higher gain can overcome the system noise and increase the sensitivity of the system. Simulation results show the proposed circuit can provide higher gain than typical structure, and just increase a little power consumption and noise. The second way uses a folded cascode LNA to reduce the supply voltage. We folded the common gate transistor to another biasing path. The supply voltage just have to bias one transistor in each biasing path. A capacitor is used to couple the RF signal between the two biasing path and make it work like a typical cascode LNA at RF. Low supply voltage also mean lower power consumption. It is an important topic of wireless communication circuit. Low power consumption can increase battery life. That will make handset device become more convenience. We simulate the proposed circuits by HSPICE. The first circuit is designed by tsmc 0.35µm CMOS process. The second circuit is designed by tsmc 0.18µm CMOS process. Both circuits are simulated with RF model. And the simulation results show all the circuit can meet the specification of LNA and achieve better performance.