Design and Implementation of parallel Structure of VLC Codec

• Main Authors: Sean Chuang, 莊智信
• Other Authors: I-Chang Jou
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/81389155379055705002

碩士 === 國立高雄第一科技大學 === 電腦與通訊工程所 === 90 === In recently, the technique of image compressing is growing up. The standard of video’s application is MPEG-1 and MPEG-2. The thesis is mainly discussing variable length codec,including the architecture, the application and the result of implementation. The architecture of variable length codec classifies serial and parallel structures. The thesis is deeply discussing both of architectures. For serial structure, it cans encode/decode one bit of codeword in one clock. And for parallel structure, it cans encode/decode one codeword regardless of length in one clock. Therefore, the parallel structure of variable length decoder is suitable for real-time system. The parallel structure of variable length codec is simulated and implemented in this thesis. The method of simulation is using Verilog Hardware Describe Language to describe circuit of the architecture and Xilinx Foundation Series 3.1i to simulate waveform. And the architecture is implemented the structure using VLSI technique. There are 992 transistors needed to implement the variable length detector.