8-bit, 80MHz Sampling Rate CMOS Pipeline Analog-to-Digital Converter

• Main Authors: Kuo-Pin Lan, 藍國斌
• Other Authors: Klaus Yung-Jane Hsu
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/15013334329443716252

碩士 === 國立清華大學 === 電子工程研究所 === 90 === It has been proved that the digital circuit is a robust and cost effective way of signal processing over the past decade, such as digital signal processors (DSP), central processor unit (CPU), and peripheral chipsets. For this reason, the digital circuit plays a more and more important role in the information application field. In addition to the computer science application, digital circuit has become more significant in the application of the multi-media and wireless communication, such as NTSC video system and 802.11a. As the portable devices becoming more popular, the battery power consumption is significant factor when designing the circuit. Besides, in order to reduce the cost, standard CMOS process is more suitable for the circuit design. Except for reducing the cost, it will improve the higher integration of the total system circuit. Thus, for meeting these requirements, it’s a better choice to design the high-speed analog-to-digital converter circuit by standard CMOS process. And it can’t consume too much power for the trend of the portable device. The objective of this research is to achieve higher transfer rate for video applications, such as camcorders and NTSC system. In order to achieve goals of low cost and high integration level, the standard digital CMOS process is employed here. Furthermore, the circuit techniques are employed here to minimize the circuit complexity and power consumption. In other words, the better way to improve the yield and cost is to implement circuit by reducing circuit complexity. Especially, it’s very popular when the circuit is designed for applications in the future. This thesis describes an 8-bit, 80MS/s pipeline analog-to-digital converter (ADC) implemented in 0.35 CMOS standard digital process. The ADC performance includes 0.44LSB DNL and 0.7LSB INL, 43.67 dB of SNDR for 38.83MHz input at 80MS/s. The power dissipation at 80MS/s full speed is 120mW. And the active area is around 1.8x1.5 mm2 (2.7mm2).