FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems

• Main Authors: Tsung-Yu Wu, 吳宗宇
• Other Authors: 林茂昭
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/72948005999977583734

碩士 === 國立清華大學 === 通訊工程研究所 === 90 === Turbo codes, which are considered as the most important research topic in the coding theory in recent yesrs, were proposed by Berrou, Glovieux, and Thitimajshima in 1993. It has a near-capacity bit error rate performance at low signal-to-noise ratios with acceptable computation complexity. A turbo decoder consists of two (or more) soft-output decodes connected by an interleaver and a deinterleaver. In this thesis, we propose a hardware structure for soft-output decoders with a unified algorithm and a two-backward-processor scheme. The unified algorithm offers a flexible structure suitable for different trellis-based soft-output algorithms. And the two-backward-processor architecture can be used to deal with the problem of long time delay. Finally, we provide a hardware design and give an example of the decoder structure for the third generation mobile communication systems.