FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems
碩士 === 國立清華大學 === 通訊工程研究所 === 90 === Turbo codes, which are considered as the most important research topic in the coding theory in recent yesrs, were proposed by Berrou, Glovieux, and Thitimajshima in 1993. It has a near-capacity bit error rate performance at low signal-to-noise ratios with accepta...
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ndltd-TW-090NTHU06500032015-10-13T10:34:06Z http://ndltd.ncl.edu.tw/handle/72948005999977583734 FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems 應用於第三代行動通訊系統軟式輸出解碼器之場式可程式邏輯閘陣列實現 Tsung-Yu Wu 吳宗宇 碩士 國立清華大學 通訊工程研究所 90 Turbo codes, which are considered as the most important research topic in the coding theory in recent yesrs, were proposed by Berrou, Glovieux, and Thitimajshima in 1993. It has a near-capacity bit error rate performance at low signal-to-noise ratios with acceptable computation complexity. A turbo decoder consists of two (or more) soft-output decodes connected by an interleaver and a deinterleaver. In this thesis, we propose a hardware structure for soft-output decoders with a unified algorithm and a two-backward-processor scheme. The unified algorithm offers a flexible structure suitable for different trellis-based soft-output algorithms. And the two-backward-processor architecture can be used to deal with the problem of long time delay. Finally, we provide a hardware design and give an example of the decoder structure for the third generation mobile communication systems. 林茂昭 楊谷章 王忠炫 趙啟超 2002 學位論文 ; thesis 38 zh-TW |
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碩士 === 國立清華大學 === 通訊工程研究所 === 90 === Turbo codes, which are considered as the most important research topic in the coding theory in recent yesrs, were proposed by Berrou, Glovieux, and Thitimajshima in 1993. It has a near-capacity bit error rate performance at low signal-to-noise ratios with acceptable computation complexity. A turbo decoder consists of two (or more) soft-output decodes connected by an interleaver and a deinterleaver. In this thesis, we propose a hardware structure for soft-output decoders with a unified algorithm and a two-backward-processor scheme. The unified algorithm offers a flexible structure suitable for different trellis-based soft-output algorithms. And the
two-backward-processor architecture can be used to deal with the
problem of long time delay. Finally, we provide a hardware design and give an example of the decoder structure for the third generation mobile communication systems.
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林茂昭 |
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林茂昭 Tsung-Yu Wu 吳宗宇 |
author |
Tsung-Yu Wu 吳宗宇 |
spellingShingle |
Tsung-Yu Wu 吳宗宇 FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems |
author_sort |
Tsung-Yu Wu |
title |
FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems |
title_short |
FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems |
title_full |
FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems |
title_fullStr |
FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems |
title_full_unstemmed |
FPGA Implementation of Soft-Output Decoders for the 3rd Generation Mobile Communication Systems |
title_sort |
fpga implementation of soft-output decoders for the 3rd generation mobile communication systems |
publishDate |
2002 |
url |
http://ndltd.ncl.edu.tw/handle/72948005999977583734 |
work_keys_str_mv |
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