| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 90 === Due to the increasing range of portable application of wireless communication within the next few years, the analog-to-digital converter(ADC) must increase their sampling rate and lower the power dissipation. A pipelined ADC which is suitable for using in parallel architecture is therefore designed for this purpose.
In this thesis, a 10-bit, 50MHz sampling rate CMOS nine-stage pipelined analog-to-digital converter is designed. Fully differential structure is used to reduce the common-mode noise. By sharing amplifiers between adjacent stages, the number of amplifiers are reduced and the power dissipation is also decreased. We use a 100MHz double sample-hold circuit as a demultiplex in front of the two channels. The overall circuit contains one front demultiplex, two 50MHz nine-stage pipelined ADCs, one multiplex and a clock generator. There are eight 1.5-bit flash ADCs, one 2-bit flash ADC, four DAC/Subtractor/Gain stage, encoder, register and adder in one channel pipelined ADC.
According to the simulation results, the nonlinearity error of the demultiplex and the first stage in pipeline ADC is within 1/2LSB, conform to the 10-bit accuracy. The integral nonlinearity error of single channel ADC is 0.6LSB. Power supply of 3V is used in this ADC chip design in order to achieve low power dissipation. The simulation results show that the power dissipation of single channel ADC is 70mW. The two input range is 1.1V~1.9V. The differential input range is from 0.8V to -0.8V. The ADC is designed with tsmc 1p5m 0.25um CMOS process. The layout area of overall circuit is 2320x2140um2 。
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