| Summary: | 碩士 === 國立海洋大學 === 電機工程學系 === 90 === Abstract
This paper describes the design of a fully integrated 2.4 GHz CMOS phase-locked loop intended for use as the frequency synthesizer for local oscillator in a mobile telecommunication receiver or transmitter.
PLL-based frequency synthesizers include a 96 divider consisted of a Master-Slave high frequency prescaler and a 48 divider which uses TSPC as D type flip-flop, a no output glitch phase/frequency detector (PFD), a charge pump (CP), a second order low pass filter uses as a loop filter (LP) and a LC-tank voltage control oscillator (VCO) having a tuning range from 2.28 to 2.42 GHz. The PFD circuit detects the phase and frequency difference between the reference signal and the feedback signal, then produces the UP and DN signals. The CP and LP circuits transfer the digital signal output from PFD to an analog signal Vc to control the output frequency of VCO. The divider employs a master-slave circuit, asynchronous and synchronous circuits to provide a 96 divider.
All circuits are designed using 0.25 um TSMC 1P5M CMOS model. The power consumption is 52.3 mW. The total chip area is 1701 × 1365 μm2.
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