| Summary: | 碩士 === 國立臺灣大學 === 工業工程學研究所 === 90 === Bottleneck machines often occur in the semiconductor manufacturing because of workload overloading, machine breakdown or any other production variability. All kinds of uncertain factors in the production line may result in bottleneck shiftiness. The throughput rate of whole system is limited by the bottlenecks. Therefore, in order to raise the throughput of the wafer fabrication, the throughput of bottleneck resources should be raised first. A methodology is proposed by this thesis, which is to use hidden capacity, to raise the capacity of bottlenecks.
Hidden capacity is the capacity, which was ignored during production planning and scheduling. Hidden capacity can be recovered with systematical coordination to raise the capacity of bottlenecks in the short term. There are many types of hidden capacity in the wafer fabrication. Three types of hidden capacity are defined by this thesis: alternative routing, maintenance rescheduling, and job rescheduling. Three economic models are developed to do capacity tuning in the short term. Using hidden capacity reduces the influence of bottleneck shift.
Therefore, there exist competitive interaction relationship among three types of hidden capacity. In order to solve the problem, an ILP model is developed, which is called integrated hidden capacity planning model. It takes the interaction relationships into consideration concurrently. The optimal solution of hidden capacity is figured out by maximizing the benefit. The robustness analysis of hidden capacity is proposed to discuss the negative effect of uncertainty between predicted and actual bottleneck information. An application procedure of hidden capacity is proposed to the enterprise, which is to use hidden capacity.
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