Low Power Counter and Divider Design

• Main Authors: Yu-Hung Yen, 顏宇宏
• Other Authors: Feipei Lai
• Format: Others
• Language: en_US
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/77198911279873165729

碩士 === 國立臺灣大學 === 資訊工程學研究所 === 90 === Low power requirement has become more and more important in recent years. Especially in portable device, power and heat becomes the most important demand when design those devices. So the basic cell library like adder, multiplier, divider, counter, ALU must be designed with the low power goal and could be used in those devices. In this thesis, we implement the low power counter and low power divider using the CMOS TSMC 0.25 technology with feature size 0.25 um and VDD = 2.25 V. In our low power counter, we achieve 11% of power reduction. And in the implementation of divider, we gain 29% power reduction when the divider iteration is operating.