| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 90 === This thesis presents a programmable filter with a self-tuning mechanism. Conformed with the DMT-VDSL system, the filter is configured as a 4th order Chebyshev low-pass filter with programmable bandwidth in which the ripple is set to 0.5~1dB. The cut-off frequencies are 1.104 × 2^n MHz, where n is 0, 1, 2, 3, 4, corresponding to different transmission rates. The filter is self-tuned by the proposed tuning mechanism that is based on the relation between DC and fundamental components of a filtered clock signal. Peak-and-Valley detection is employed to observe the two frequency components in time domain. Implemented in 0.35µm 1P4M digital CMOS technology, the circuit occupies an area of 1.8 × 1.8mm^2. According to the post-layout simulation, it achieves -55dB THD using 2V supply voltage while the output swing is 120mVpp. The power consumption for the core filter is 2.8mW, whereas the overall system, including the filter, the output buffer, and the tuning circuits, consumes 28mW power.
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