Design and Application of Delay-Locked Loop

• Main Authors: CHOU YEN YNN, 周彥云
• Other Authors: 陳凰美
• Format: Others
• Language: zh-TW
• Published: 2002
• Online Access: http://ndltd.ncl.edu.tw/handle/94975998325650320235

碩士 === 國立臺灣科技大學 === 電子工程系 === 90 === With the rapid advances in semiconductor technologies, modern digital system operated at several hundred megahertz have been successfully developed. The clock-skew problem has also becomes one of the bottlenecks for high-performace system. Delay-locked loop(DLL) have been widely adopted to solve the clock-skew problem. This thesis is mainly dedicated to discuss the design and application of CMOS DLL. In this thesis, several architecture of delay locked loop are introduced.A binary search algorithm delay locked loop is present to realize a fast-lock buffer by 0.35μm CMOS process. This DLL uses a binary search method to insert an optimum delay between input clock and output clock for compensating the skew by process, voltage, temperature and length of transmission line. And because of a triple-modulus frequency divider, this DLL can select optimum lock time depend on feedback response. From simulation result, we have demonstrated that the lock time of SARDLL is within 30 clock cycles at 100-MHz input clcok. The power dissipation is 32mW at a 2-V supply voltage while rms jitter is 13.6ps.