| Summary: | 碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 90 === Cache coherence problem is a major concern on shared-memory multiprocessors system. Hardware solution of cache coherence schemes for large-scale shared-memory multiprocessor cost much complexity and expensive when the processors increase. So the software cache coherence schemes have been proposed. But pure software cache coherence schemes have their limitation on performance so that software cache coherence hardware support schemes have been addresses. Reducing memory traffic, memory references and hardware cost are their advantages. They insert some cache management instructions to maintain cache coherence in the program at the compiler-time. But the behavior of program and other factors can affect the performance of software cache coherence schemes. Previously studying on the schemes focus on Doall-type loop and serial code segment. In this thesis, we focus on Doacross-type loop, analysis and improve some schemes. Finally, we propose new software cache coherence scheme to overcome Doacross loop.
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