The VLSI Architecture Design of the Block Coding Algorithm for JPEG2000

碩士 === 淡江大學 === 電機工程學系 === 90 === As the progressing of the development of communication and multimedia, image data compression is getting important nowadays. People need high quality image, and the conventional JPEG still image compression standard does not satisfy this requirement any m...

Full description

Bibliographic Details
Main Authors: Yu-Sen Lin, 林于森
Other Authors: Jen-Shiun Chiang
Format: Others
Language:zh-TW
Published: 2002
Online Access:http://ndltd.ncl.edu.tw/handle/80494564292953429474
Description
Summary:碩士 === 淡江大學 === 電機工程學系 === 90 === As the progressing of the development of communication and multimedia, image data compression is getting important nowadays. People need high quality image, and the conventional JPEG still image compression standard does not satisfy this requirement any more. Therefore JPEG2000 is invented to fit for the requirement. However, JPEG2000 needs more complicated computation than the conventional JPEG, especially the entropy coding part. In JPEG2000 the entropy coding is accomplished by EBCOT algorithm. Due to the complication of the EBCOT algorithm it is almost impossible to implement it in software approach in real time, it needs to be implemented by dedicated hardware. In order to accelerate the encoding process of EBCOT algorithm, this thesis proposes an efficient architecture composed of pass-parallel context modeling scheme and low-cost pass switching arithmetic encoder (PSAE) for EBCOT entropy encoder. The pass-parallel context modeling scheme merges the three coding passes of fractional bit-plane coding process into a single pass to improve the system performance. Instead of using three arithmetic encoders, the PSAE needs only one arithmetic encoder, and thus reduces the hardware cost. The proposed architecture therefore has three main advantages: 1) fast computation, 2) low internal memory accesses, and 3) compared with the conventional architectures it reduces 4K bits of internal memories. The experimental results show that the proposed architecture reduces the processing time by more than 25% compared with the previous methods. Finally, a prototyping chip of context modeling module is implemented based on TSMC 0.35μm CMOS technology to verify the proposed architecture. Simulation results show that the maximum operation frequency is 100MHz and the average power dissipation is 45mW.