An efficient adder-based 2-D DCT/IDCT IP core design
碩士 === 國立中正大學 === 資訊工程研究所 === 91 ===
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| Format: | Others |
| Language: | zh-TW |
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2003
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| Online Access: | http://ndltd.ncl.edu.tw/handle/58577354836897901875 |
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ndltd-TW-091CCU00392065 |
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oai_dc |
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ndltd-TW-091CCU003920652016-06-24T04:15:34Z http://ndltd.ncl.edu.tw/handle/58577354836897901875 An efficient adder-based 2-D DCT/IDCT IP core design 以加法為基礎之高效能二維離散餘弦/反餘弦轉換數位矽智財核心設計 朱瑞欽 碩士 國立中正大學 資訊工程研究所 91 郭峻因 2003 學位論文 ; thesis 47 zh-TW |
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NDLTD |
| language |
zh-TW |
| format |
Others
|
| sources |
NDLTD |
| description |
碩士 === 國立中正大學 === 資訊工程研究所 === 91 ===
|
| author2 |
郭峻因 |
| author_facet |
郭峻因 朱瑞欽 |
| author |
朱瑞欽 |
| spellingShingle |
朱瑞欽 An efficient adder-based 2-D DCT/IDCT IP core design |
| author_sort |
朱瑞欽 |
| title |
An efficient adder-based 2-D DCT/IDCT IP core design |
| title_short |
An efficient adder-based 2-D DCT/IDCT IP core design |
| title_full |
An efficient adder-based 2-D DCT/IDCT IP core design |
| title_fullStr |
An efficient adder-based 2-D DCT/IDCT IP core design |
| title_full_unstemmed |
An efficient adder-based 2-D DCT/IDCT IP core design |
| title_sort |
efficient adder-based 2-d dct/idct ip core design |
| publishDate |
2003 |
| url |
http://ndltd.ncl.edu.tw/handle/58577354836897901875 |
| work_keys_str_mv |
AT zhūruìqīn anefficientadderbased2ddctidctipcoredesign AT zhūruìqīn yǐjiāfǎwèijīchǔzhīgāoxiàonéngèrwéilísànyúxiánfǎnyúxiánzhuǎnhuànshùwèixìzhìcáihéxīnshèjì AT zhūruìqīn efficientadderbased2ddctidctipcoredesign |
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