An efficient adder-based 2-D DCT/IDCT IP core design

An efficient adder-based 2-D DCT/IDCT IP core design

碩士 === 國立中正大學 === 資訊工程研究所 === 91 ===

Bibliographic Details
Main Author:	朱瑞欽
Other Authors:	郭峻因
Format:	Others
Language:	zh-TW
Published:	2003
Online Access:	http://ndltd.ncl.edu.tw/handle/58577354836897901875

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