Multiobjective-Driven Floorplan on DBL Representation

• Main Author: 廖祥智
• Other Authors: 顏金泰
• Format: Others
• Language: zh-TW
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/10274946301721304758

碩士 === 中華大學 === 資訊工程學系碩士班 === 91 === Due to the coming of new system-on-chip (SoC) age, silicon-intellectual- property (SIP) modules become popular for modern chip design. Since SIP modules in one chip have provided by different companies or departments, it is very important for the development of SoC chip to integrate all the SIP modules into a single chip. On the other hand, to deal with the increasing complexity and various requirements of including chip performance, low power …etc of circuit, it also makes one floorplan to become more critical than even. However, an effective better floorplan approach depends on the data representation of floorplans, the estimation of cost function, and the development of floorplan improvement approach. In this paper, we discuss how to solve the non-slicing floorplan problem for multiple objectives. We use one data representation, named double -bound-list (DBL) for non-slicing floorplans. The DBL representation combines the advantages of representative popular representations such as sequence pair, O-tree and B*-tree. From the structure of the DBL representation, the floorplan area and the geometric adjacent relationship can be immediately found. In addition, the DBL representation uses less memory for the storage of one non-slicing floorplan. Now, there is not only the discussion of area requirement discussion for the non-slicing floorplan problem, but also the discussion of the high performance requirement, maximum routability requirement … etc. Especially, for routability requirement, there is more difficulty to guarantee the routabililty property in the routing phase due to the increasing complexity of net connections in circuit design. Based on the combination of multiple critical objectives, it takes much time to search optimal non-slicing floorplan results. Therefore, we use a data structure, named Hierarchical Stair Contour (HSC), to store the contour of an incremental floorplan, and improve the search efficiency. Finally, we develop a simulated-annealing-based floorplan approach on the proposed DBL and HSC data structure to obtain a final non-slicing floorpaln result. The experimental results show that the proposed approach can obtain better multiobjective floorplan results.