Gate Dielectrics and Cell Membrane Studies for La2O3/ Si0.3Ge0.7 p-MOSFETs and Biologic Cells

• Main Authors: Chien Hung Wu, 吳建宏
• Other Authors: I. J. Hsieh
• Format: Others
• Language: en_US
• Published: 2003
• Online Access: http://ndltd.ncl.edu.tw/handle/93173986312247825936

碩士 === 中華大學 === 電機工程學系碩士班 === 91 === We have developed high K La2O3 gate dielectrics by a simple process using direct thermal oxidization of deposited La. The dielectric integrity improves as decreasing La2O3 thickness because of the applied low oxidation temperature. From the measured capacitance, the 60Å La2O3 has a K value of 27 that has an equivalent oxide thickness of 8.7Å. This high K is further evidenced from MOSFET’s high current drive and transconductance with low off-state current. Low stress-induced leakage current and high charge-to-breakdown comparable with SiO2 are obtained that demonstrates excellent reliability. The achieved low equivalent oxide thickness is due to the high thermodynamic stability on Si and also stable for hydrogen annealing up to 550oC. At the same time, it is developed a new approach to form epitaxial SiGe layer .The epitaxial SiGe was formed by the deposition of amorphous Ge layer and subsequent high temperature annealing through the mechanism of solid phase epitaxy. It was found that the existence of native oxide plays a critical role in the quality of SiGe layer. To evaluate the feasibility of this SiGe layer in practical applications, we have fabricated SiGe channel MOSFET's. However, this result is much different from that in the previous reporters. SiGe layer formed in this method is a relaxed material and may not suffer from the strain-relaxation related problems in the high temperature oxidation step. Therefore, we have successfully integrated two techniques into current VLSI technology to fabricate SiGe cham1el PMOSFET's with high k dielectric. It manifests batter current drive capability and batter subthreshold swing. More important, this approach is simple, less expensive and fully compatible with current VLSI tech1ology. In the future, according to the continuous scaling down of device, the thickness of gate oxide has to be reduced. The thickness of gate oxide will be decreased to the limitation. It also has been investigated into the feasibility of the biological cell, in order to substitute for gate dielectric. Then it is experimenting with the relationship between the cell and the electric field.