Timing Driven Quadrisection Partition-Based Standard Cell Placement VLSI Design
碩士 === 中原大學 === 資訊工程研究所 === 91 === As the semiconductor proceeding technology enters deep submicron era, the timing-driven placement approach for very large circuits becomes more important. This paper presents a timing-driven quadrisection partition-based placement for VLSI standard cell circuit. T...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2003
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/09442122979883131716 |