| Summary: | 碩士 === 中原大學 === 電機工程研究所 === 91 === Abstract
In this thesis, we use common sub-expression elimination for reducing hardware in FIR filters design. We adapt five-term common sub-expression elimination to replace the existent three-term common sub-expression for FIR filters design to improve its performance. The results of simulation show that this method saves 18.5% adders in FPGA implementation. In addition, by removing the redundant carry bits, the number of gate counts in FIR filters design will be much reduced. The results of simulation show that such an approach saves 42% gate counts in FPGA implementations.
First, at tradition, the sub-expression method used to transform this filter implementation relies upon the fact that all canonical signed digit (CSD) coefficients can be built using 3 simples’ sub-expression. In our research, it finds out that three-term sub-expression elimination repeated many times. Hence, we add another two terms to form the five-term common sub-expression elimination to improve the hardware performance. The results of simulation show that this method reduces adders from 54 to 44 in FPGA implementation for a 53-tap FIR filter.
Second, traditionally, the design of a 1-bit binary adder can be accomplished output bit number adder 1-bit. According to this fact, a method that uses characteristic of constant coefficients to reduce output bit number is proposed. By removing the redundant carry bits, the number of gate counts in FIR filters design will be much reduced. However, from our research, we find that the proposed method can reduce both adders and hardware gate count numbers. The results of simulation show that 42% gate counts is saved in FPGA implementations for a 53-tap FIR filter.
There are three distinguished research results of the common sub-expression elimination in this thesis that are stated as follows:
(1) Using five-term common sup-expression elimination to reduce 18.5% adders.
(2) Using characteristic of constant coefficients to reduce output bit number such that 42% gate counts reduce is saved in FPGA implementation.
(3) Adapting Xilinx Vertex v600FG680-6 in FPGA implantation to save hardware resources.
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