| Summary: | 碩士 === 逢甲大學 === 自動控制工程所 === 91 === In recent years, Orthogonal Frequency Division Multiplexing (OFDM) technology has attracted attention in wireless communication system. Because it can offer high-quality audio services, it is mentioned in 4G standard. Then, many researchers have been devoted to the research and development of low cost mobile phone products. In the modulator and demodulator part of OFDM, the Fast Fourier Transform (FFT) is key component which is very suitable for Application-Specific Integration Circuit (ASIC) implementation. Previously, the major concern was the processing speed, but the power consumption has become more important in recent years. This thesis focuses on exploring efficient solutions for hardware power consumption of FFT processor. It can reduce the twiddle factor access using a new ordering of FFT butterfly technique. Finally, the proposed architecture, 8060 logic cell were consumed roughly for 40MHz operating clock.
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