| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === The ALU (Arithmetic Logic Unit) and multiplier are main elements of CPU. These perform all the operations required by CPU instructions, and dissipate much of the power consumption in CPU. If we reduce the power consumption of these two elements, we can achieve low power CPU.
In this thesis, we present two novel low power methods to implement the ALU and 4-2 compressor which used in multiplier, respectively. One is to abandon the “don’t care” condition in decoder of ALU. This method does not divide signal path into logical and arithmetic paths thus can achieve low power consumption and improve performance by reducing the number of transistors. The other one applied in modified Booth multiplier is using balance delay paths for 4-2 compressor. The glitches generated in our 4-2 compressor can be reduced, thus the power consumption can be reduced. The critical path delay is decreased because the load capacitances of internal nodes are smaller than previous method.
Moreover, we use these methods to construct ALU and 4-2 compressor with TSMC 0.25 μm cell library. Experimental results show the new ALU and 4-2 compressor have lower power consumption and higher performance than that of previous ones.
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