Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem
碩士 === 國立交通大學 === 工業工程與管理系 === 91 === The integrated circuit packaging scheduling problem (ICPSP) is a variation of the flexible flow shop scheduling problem, which represents a generalization of the traditional flow shop and the identical parallel machine problem. In the multi-stage integrated cir...
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ndltd-TW-091NCTU00310512016-06-22T04:14:05Z http://ndltd.ncl.edu.tw/handle/24647916933547815076 Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem 多階段IC封裝排程問題--以演算法為基礎之解決方案 Yung-Hsuan Chen 陳勇亘 碩士 國立交通大學 工業工程與管理系 91 The integrated circuit packaging scheduling problem (ICPSP) is a variation of the flexible flow shop scheduling problem, which represents a generalization of the traditional flow shop and the identical parallel machine problem. In the multi-stage integrated circuit (IC) packaging factories, the jobs are clustered by their product types and carry with multiple operations, which must be processed on a series of identical parallel machines according to the processing sequences and be completed before due dates. Further, the job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. Since the ICPSP involves constraints on job product types, product-type dependent processing time, due date restrictions, machine capacity, sequentially dependent setup time, and manufacturing sequences, it is more difficult to solve than the classical flexible flow shop problem. In this research, we consider the ICPSP and propose four strategies to solve multi-stage processing with feasible planning for the objective of minimizing the total machine workload. We integrate saving-based algorithms into our strategies in order to minimize the total setup time of machines, which is the essential of minimizing total machine workload, and reduce the total numbers of setup at each stage with feasible solutions. We apply well-known saving-based algorithms and develop new savings function for modifications for obtaining better solution in the ICPSP. To demonstrate the feasibility of strategies, a set of test problems is designed, which involves the following four factors, the product family ratio at critical stage, the tightness of due dates, the setup time level at critical stage, and the level of total processing time. Computational results from running the designed test problems demonstrate that the feasibility of strategies and the performance of the three proposed modified savings algorithms significantly outperform the original savings algorithm. Wen-Lea Pearn Shu-Hsing Chung 彭文理 鍾淑馨 2003 學位論文 ; thesis 46 en_US |
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碩士 === 國立交通大學 === 工業工程與管理系 === 91 === The integrated circuit packaging scheduling problem (ICPSP) is a variation of the flexible flow shop scheduling problem, which represents a generalization of the traditional flow shop and the identical parallel machine problem. In the multi-stage integrated circuit (IC) packaging factories, the jobs are clustered by their product types and carry with multiple operations, which must be processed on a series of identical parallel machines according to the processing sequences and be completed before due dates. Further, the job processing time depends on the product type, and the machine setup time is sequentially dependent on the orders of jobs processed. Since the ICPSP involves constraints on job product types, product-type dependent processing time, due date restrictions, machine capacity, sequentially dependent setup time, and manufacturing sequences, it is more difficult to solve than the classical flexible flow shop problem. In this research, we consider the ICPSP and propose four strategies to solve multi-stage processing with feasible planning for the objective of minimizing the total machine workload. We integrate saving-based algorithms into our strategies in order to minimize the total setup time of machines, which is the essential of minimizing total machine workload, and reduce the total numbers of setup at each stage with feasible solutions. We apply well-known saving-based algorithms and develop new savings function for modifications for obtaining better solution in the ICPSP. To demonstrate the feasibility of strategies, a set of test problems is designed, which involves the following four factors, the product family ratio at critical stage, the tightness of due dates, the setup time level at critical stage, and the level of total processing time. Computational results from running the designed test problems demonstrate that the feasibility of strategies and the performance of the three proposed modified savings algorithms significantly outperform the original savings algorithm.
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Wen-Lea Pearn |
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Wen-Lea Pearn Yung-Hsuan Chen 陳勇亘 |
author |
Yung-Hsuan Chen 陳勇亘 |
spellingShingle |
Yung-Hsuan Chen 陳勇亘 Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
author_sort |
Yung-Hsuan Chen |
title |
Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
title_short |
Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
title_full |
Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
title_fullStr |
Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
title_full_unstemmed |
Algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
title_sort |
algorithms-based solution for multi-stage integrated circuit packaging scheduling problem |
publishDate |
2003 |
url |
http://ndltd.ncl.edu.tw/handle/24647916933547815076 |
work_keys_str_mv |
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